SN74AUP1G80YFPR
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFBGA, DSBGA |
| Number of Pins | 6 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.4mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Number of Outputs | 1 |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Load Capacitance | 30pF |
| Number of Bits | 1 |
| Clock Frequency | 257MHz |
| Propagation Delay | 6.4 ns |
| Turn On Delay Time | 3.1 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Prop. Delay@Nom-Sup | 28.7 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 500μm |
| Length | 1mm |
| Width | 1.4mm |
| Thickness | 500μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP1G80YFPR Overview
The package is in the form of 6-XFBGA, DSBGA. It is contained within the Tape & Reel (TR)package. Invertedis the output configured for it. It is configured with the trigger Positive Edge. There is an electronic component mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 0.8V~3.6V. It is operating at a temperature of -40°C~85°C TA. This electronic flip flop is of type D-Type. It belongs to the 74AUPseries of FPGAs. This D flip flop should not have a frequency greater than 257MHz. As a result, it consumes 500nA quiescent current. The number of terminations is 6. JK flip flop belongs to 74AUP1G80 family. The D flip flop is powered by a voltage of 1.2V . A 1.5pFfarad input capacitance is provided by this T flip flop. AUP/ULP/Vis the family of this D flip flop. In this case, the electronic component is mounted in the way of Surface Mount. There are 6pins on it. There is a clock edge trigger type of Positive Edgeon this device. It is part of the FF/Latchesbase part number family. The flip flop is designed with 1bits. A normal operating voltage (Vsup) should remain above 0.8V. This D flip flop is well suited for TR based on its reliable performance.
SN74AUP1G80YFPR Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
SN74AUP1G80YFPR Applications
There are a lot of Texas Instruments SN74AUP1G80YFPR Flip Flops applications.
- Set-reset capability
- Load Control
- EMI reduction circuitry
- Synchronous counter
- Single Up Count-Control Line
- Registers
- Differential Individual
- Dynamic threshold performance
- Data storage
- ATE