SN74ALVCH16820DGGR
| Parameters | |
|---|---|
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Number of Pins | 56 |
| Weight | 252.792698mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74ALVCH |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Discontinued |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74ALVCH16820 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Number of Circuits | 2 |
| Number of Ports | 2 |
| Output Current | 24mA |
| Clock Frequency | 150MHz |
| Propagation Delay | 5.5 ns |
| Quiescent Current | 40μA |
| Turn On Delay Time | 1 ns |
| Family | ALVC/VCX/A |
| Logic Function | D-Type, Flip-Flop |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 4.8ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.8 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Power Supply Current-Max (ICC) | 0.04mA |
| Number of Output Lines | 3 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 1.2mm |
| Length | 14mm |
| Width | 6.1mm |
| Thickness | 1.15mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74ALVCH16820DGGR Overview
It is embeded in 56-TFSOP (0.240, 6.10mm Width) case. D flip flop is included in the Cut Tape (CT)package. As configured, the output uses Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates with an input voltage of 1.65V~3.6V volts. In the operating environment, the temperature is -40°C~85°C TA. D-Typeis the type of this D latch. This type of FPGA is a part of the 74ALVCH series. It should not exceed 150MHzin terms of its output frequency. A total of 1elements are present in it. There have been 56 terminations. If you search by 74ALVCH16820, you will find similar parts. A voltage of 1.8V is used to power it. Its input capacitance is 3.5pFfarads. It is a member of the ALVC/VCX/Afamily of D flip flop. It is mounted in the way of Surface Mount. 56pins are included in its design. This device exhibits a clock edge trigger type of Positive Edge. There is a base part number FF/Latchesfor the RS flip flops. Using 2 circuits, it is highly flexible. This D flip flop is well suited for TR based on its reliable performance. There are 2 ports embedded in the flip flops. As a result of its output current of 24mA, it is very flexible in terms of design. There are no output lines on the JK flip flop. There is a consumption of 40μAof quiescent current from it.
SN74ALVCH16820DGGR Features
Cut Tape (CT) package
74ALVCH series
56 pins
SN74ALVCH16820DGGR Applications
There are a lot of Texas Instruments SN74ALVCH16820DGGR Flip Flops applications.
- Storage Registers
- Safety Clamp
- Instrumentation
- Functionally equivalent to the MC10/100EL29
- Common Clocks
- Balanced Propagation Delays
- Guaranteed simultaneous switching noise level
- Automotive
- Shift registers
- Individual Asynchronous Resets