| Parameters |
| Mount |
Through Hole |
| Mounting Type |
Through Hole |
| Package / Case |
16-DIP (0.300, 7.62mm) |
| Number of Pins |
16 |
| Weight |
4.535924g |
| Operating Temperature |
-55°C~125°C TA |
| Packaging |
Tube |
| Published |
2009 |
| Series |
4000B |
| JESD-609 Code |
e3 |
| Pbfree Code |
yes |
| Part Status |
Obsolete |
| Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
| Number of Terminations |
16 |
| Type |
D-Type |
| Terminal Finish |
Tin (Sn) |
| Subcategory |
FF/Latches |
| Packing Method |
RAIL |
| Technology |
CMOS |
| Voltage - Supply |
3V~18V |
| Terminal Position |
DUAL |
| Peak Reflow Temperature (Cel) |
260 |
| Supply Voltage |
5V |
| Time@Peak Reflow Temperature-Max (s) |
40 |
| Base Part Number |
4076 |
| Function |
Master Reset |
| Output Type |
Tri-State, Non-Inverted |
| Number of Elements |
1 |
| Polarity |
Non-Inverting |
| Supply Voltage-Min (Vsup) |
3V |
| Load Capacitance |
50pF |
| Output Current |
8.8mA |
| Number of Bits |
4 |
| Clock Frequency |
12MHz |
| Propagation Delay |
600 ns |
| Turn On Delay Time |
600 ns |
| Current - Quiescent (Iq) |
20μA |
| Current - Output High, Low |
8.8mA 8.8mA |
| Number of Gates |
4 |
| Max Propagation Delay @ V, Max CL |
180ns @ 15V, 50pF |
| Trigger Type |
Positive Edge |
| Input Capacitance |
5pF |
| Number of Output Lines |
3 |
| fmax-Min |
6 MHz |
| Clock Edge Trigger Type |
Positive Edge |
| Height |
3.43mm |
| Length |
19.55mm |
| Width |
6.85mm |
| Radiation Hardening |
No |
| REACH SVHC |
No SVHC |
| RoHS Status |
RoHS Compliant |
| Lead Free |
Lead Free |
MC14076BCPG Overview
The package is in the form of 16-DIP (0.300, 7.62mm). It is included in the package Tube. Currently, the output is configured to use Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. Through Holemounts this electrical part. The JK flip flop operates with an input voltage of 3V~18V volts. Temperature is set to -55°C~125°C TA. This D latch has the type D-Type. In terms of FPGAs, it belongs to the 4000B series. Its output frequency should not exceed 12MHz Hz. A total of 1 elements are present. T flip flop consumes 20μA quiescent energy. A total of 16terminations have been recorded. The object belongs to the 4076 family. A voltage of 5V provides power to the D latch. Its input capacitance is 5pF farads. There is an electronic part mounted in the way of Through Hole. 16pins are included in its design. There is a clock edge trigger type of Positive Edgeon this device. This device is part of the FF/Latchesbase part number family. It is designed with a number of bits of 4. For normal operation, the supply voltage (Vsup) should be kept above 3V. As a result of its reliable performance, this T flip flop is suitable for RAIL. With a current output of 8.8mA , it offers maximum design flexibility. There are 3 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code. In its basic building block, there are 4 gates.
MC14076BCPG Features
Tube package
4000B series
16 pins
4 Bits
4 gates
MC14076BCPG Applications
There are a lot of ON Semiconductor MC14076BCPG Flip Flops applications.
- Buffer registers
- Shift registers
- High Performance Logic for test systems
- Pattern generators
- Bus hold
- Frequency division
- CMOS Process
- Latch
- Set-reset capability
- ESD performance