MC100EP131FAR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 32-LQFP |
| Number of Pins | 32 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Published | 2006 |
| Series | 100EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 32 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn80Pb20) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | 3V~5.5V |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.8mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EP131 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 4 |
| Clock Frequency | 3GHz |
| Propagation Delay | 600 ps |
| Turn On Delay Time | 460 ps |
| Logic Function | AND, Flip-Flop |
| Number of Bits per Element | 1 |
| Trigger Type | Positive Edge |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 7mm |
| Width | 7mm |
| Radiation Hardening | No |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC100EP131FAR2 Overview
In the form of 32-LQFP, it has been packaged. Package Cut Tape (CT)embeds it. It is configured with Differentialas an output. It is configured with a trigger that uses a value of Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. A voltage of 3V~5.5Vis used as the supply voltage. A temperature of -40°C~85°C TAis used in the operation. It belongs to the type D-Typeof flip flops. In FPGA terms, D flip flop is a type of 100EPseries FPGA. It should not exceed 3GHzin terms of its output frequency. There are 32 terminations,D latch belongs to the 100EP131 family. A voltage of 3.3V provides power to the D latch. This electronic part is mounted in the way of Surface Mount. 32pins are included in its design. It has a clock edge trigger type of Positive Edge. This part is included in FF/Latches. It reaches the maximum supply voltage (Vsup) at 5.5V. The supply voltage (Vsup) should be maintained above 3V for normal operation. The superior flexibility of this circuit is achieved by using 4 circuits. In view of its reliability, this D flip flop is a good fit for TAPE AND REEL. Additionally, it is characterized by NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC100EP131FAR2 Features
Cut Tape (CT) package
100EP series
32 pins
MC100EP131FAR2 Applications
There are a lot of ON Semiconductor MC100EP131FAR2 Flip Flops applications.
- Reduced system switching noise
- Functionally equivalent to the MC10/100EL29
- Buffer registers
- Computing
- Single Down Count-Control Line
- ESD protection
- Count Modes
- Safety Clamp
- Digital electronics systems
- Balanced 24 mA output drivers