EPM7256AEFC256-5
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 256-BGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | MAX® 7000A |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 256 |
| ECCN Code | 3A991 |
| Terminal Finish | TIN LEAD |
| Additional Feature | YES |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | EPM7256 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 2.5/3.33.3V |
| Supply Voltage-Min (Vsup) | 3V |
| Programmable Type | In System Programmable |
| Number of I/O | 164 |
| Clock Frequency | 172.4MHz |
| Propagation Delay | 5.5 ns |
| Number of Gates | 5000 |
| Output Function | MACROCELL |
| Number of Macro Cells | 256 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Delay Time tpd(1) Max | 5.5ns |
| Number of Logic Elements/Blocks | 16 |
| Height Seated (Max) | 2.1mm |
| Length | 17mm |
| Width | 17mm |
| RoHS Status | Non-RoHS Compliant |
EPM7256AEFC256-5 Overview
Currently, there are 256 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.It is part of the 256-BGA package.There are 164 I/Os on the board.It is programmed that device terminations will be 256 .Its terminal position is BOTTOM.The power supply voltage is 3.3V.It belongs to the family [0].The chip should be packaged by Tray.Ensure its reliability by operating at [0].It is recommended that Surface Mountholds the chip in place.This type of FPGA is a part of the MAX? 7000A series.This device is also capable of displaying [0].The EPM7256contains its related parts.A digital circuit is built using 5000gates.A total of 16logic elements/blocks are present.Currently, it is powered by 2.5/3.33.3Vsources.A maximum supply voltage (Vsup) of 3.6V is provided.If the supply voltage (Vsup) is greater than 3V, then the device will work properly.clock frequency should not exceed [0].
EPM7256AEFC256-5 Features
256-BGA package
164 I/Os
The operating temperature of 0°C~70°C TA
2.5/3.33.3V power supplies
EPM7256AEFC256-5 Applications
There are a lot of Intel EPM7256AEFC256-5 CPLDs applications.
- Address decoders
- Preset swapping
- TIMERS/COUNTERS
- Digital designs
- STANDARD SERIAL INTERFACE UART
- Field programmable gate
- Power automation
- Multiple Clock Source Selection
- Software-driven hardware configuration
- Boolean function generators