EPM7128AEFC100-5
| Parameters | |
|---|---|
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Package / Case | FBGA |
| Number of Pins | 100 |
| Published | 1998 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 100 |
| ECCN Code | 3A991 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 235 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1mm |
| Frequency | 250MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 100 |
| Number of Outputs | 84 |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 84 |
| Memory Type | EEPROM |
| Propagation Delay | 5 ns |
| Turn On Delay Time | 5 ns |
| Frequency (Max) | 192.3MHz |
| Architecture | PAL-TYPE |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Programmable I/O | 84 |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 5 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 1.7mm |
| Length | 11mm |
| Width | 11mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
EPM7128AEFC100-5 Overview
There are 128 macro cells, which provide radio coverage via high-power cell towers, antennas or masts in a mobile phone network.A FBGA package contains the item.The device has 84inputs and outputs.There are 100 terminations programmed into the device.This electrical part has a terminal position of BOTTOMand is connected to the ground.Power is supplied by a voltage of 3.3V volts.There is a part in the family [0].There are 100 pins on the chip.A digital circuit is built using 2500gates.High efficiency requires the supply voltage to be maintained at [0].Data storage is performed using [0].The electronic part is mounted by Surface Mount.There are 100 pins on the device.With a maximum supply voltage of [0], it operates.Initially, it requires a voltage of 3Vas the minimum supply voltage.In total, there are 84programmable I/Os.It is possible to achieve a frequency of 250MHz.Ideally, the operating temperature should be greater than 0°C.It is recommended that the operating temperature be below 70°C.It is composed of 8 logic blocks (LABs).There should be a lower maximum frequency than 192.3MHz.Types of programmable logic are divided into EE PLD.The device is configured with an output of [0].
EPM7128AEFC100-5 Features
FBGA package
84 I/Os
100 pin count
100 pins
8 logic blocks (LABs)
84 outputs
EPM7128AEFC100-5 Applications
There are a lot of Altera EPM7128AEFC100-5 CPLDs applications.
- I/O expansion
- Handheld digital devices
- Bootloaders for FPGAs
- POWER-SAVING MODES
- Parity generators
- Battery operated portable devices
- Timing control
- Digital multiplexers
- INTERRUPT SYSTEM
- Custom state machines