AM3358BZCZA100
| Parameters | |
|---|---|
| Memory Type | Cache, RAM, ROM |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | ARM® Cortex®-A8 |
| Supply Current-Max | 400mA |
| Bit Size | 32 |
| Data Bus Width | 32b |
| Core Architecture | ARM |
| Boundary Scan | YES |
| Low Power Mode | YES |
| Format | FIXED POINT |
| Integrated Cache | YES |
| Voltage - I/O | 1.8V 3.3V |
| Number of UART Channels | 6 |
| Ethernet | 10/100/1000Mbps (2) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | Yes |
| RAM Controllers | LPDDR, DDR2, DDR3, DDR3L |
| USB | USB 2.0 + PHY (2) |
| Additional Interfaces | CAN, I2C, McASP, McSPI, MMC/SD/SDIO, UART |
| Co-Processors/DSP | Multimedia; NEON™ SIMD |
| Number of Cores | 1 |
| Security Features | Cryptography, Random Number Generator |
| Display & Interface Controllers | LCD, Touchscreen |
| Height | 1.4mm |
| Length | 15mm |
| Width | 15mm |
| Thickness | 900μm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Copper, Silver, Tin |
| Package / Case | 324-LFBGA |
| Surface Mount | YES |
| Number of Pins | 324 |
| Weight | 1.713814g |
| Operating Temperature | -40°C~105°C TJ |
| Packaging | Tray |
| Series | Sitara™ |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 324 |
| ECCN Code | 5A992.C |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | Microprocessors |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.325V |
| Terminal Pitch | 0.8mm |
| Frequency | 1GHz |
| Base Part Number | AM3358 |
| Voltage | 1.144V |
| Interface | CAN, Ethernet, I2C, SPI, UART, USB |
| Max Supply Voltage | 1.378V |
| Min Supply Voltage | 912mV |
| RAM Size | 64kB |
M3358BZCZA100 Description
AM3358BZCZA100 microprocessors are based on ARM Cortex-A8 processors and are enhanced with image, graphics processing, peripherals, and industrial interface options such as EtherCAT and PROFIBUS. These devices support Advanced operating system (HLOS). Processors SDK Linux and TI-RTOS are available free of charge from TI. The AM335x microprocessor includes the subsystems shown in the functional block diagram, and each subsystem is briefly described: the microprocessor unit subsystem is based on the ARM Cortex-A8 processor, and the PowerVR SGX graphics accelerator subsystem provides 3D graphics acceleration to support display and game effects. PRU-ICSS is separated from the ARM kernel and allows independent operation and timing for greater efficiency and flexibility. PRU-ICSS supports other peripheral interfaces and real-time protocols, such as EtherCAT, PROFINET, Ethernet / IP, PROFIBUS, Ethernet Powerlink, SERCOS, etc. In addition, PRU-ICSS 's programmability and access to pins, events, and all system-on-a-chip (SoC) resources provide flexibility for fast real-time response, specialized data processing operations, customized peripheral interfaces, and offloading tasks from other processor cores of SoC.
AM3358BZCZA100 Features
? Up to 1-GHz Sitara? ARM? Cortex?
-A8 32?Bit
RISC Processor
– NEON? SIMD Coprocessor
– 32KB of L1 Instruction and 32KB of Data Cache
With Single-Error Detection (Parity)
– 256KB of L2 Cache With Error Correcting Code
(ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
– Emulation and Debug - JTAG
– Interrupt Controller (up to 128 Interrupt
Requests)
? On-Chip Memory (Shared L3 RAM)
– 64KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– Accessible to All Masters
– Supports Retention for Fast Wakeup
? External Memory Interfaces (EMIF)
– mDDR(LPDDR), DDR2, DDR3, DDR3L
Controller:
– mDDR: 200-MHz Clock (400-MHz Data Rate)
– DDR2: 266-MHz Clock (532-MHz Data Rate)
– DDR3: 400-MHz Clock (800-MHz Data Rate)
– DDR3L: 400-MHz Clock (800-MHz Data
Rate)
– 16-Bit Data Bus
– 1GB of Total Addressable Space
– Supports One x16 or Two x8 Memory Device
Configurations
– General-Purpose Memory Controller (GPMC)
– Flexible 8-Bit and 16-Bit Asynchronous
Memory Interface With up to Seven Chip
Selects (NAND, NOR, Muxed-NOR, SRAM)
– Uses BCH Code to Support 4-, 8-, or 16-Bit
ECC
– Uses Hamming Code to Support 1-Bit ECC
– Error Locator Module (ELM)
– Used in Conjunction With the GPMC to
Locate Addresses of Data Errors from
Syndrome Polynomials Generated Using a
BCH Algorithm
– Supports 4-, 8-, and 16-Bit per 512-Byte
Block Error Location Based on BCH
AM3358BZCZA100 Applications
? Connected Vending Machines
? Weighing Scales
? Educational Consoles
? Advanced Toys
? Gaming Peripherals
? Home and Industrial Automation
? Consumer Medical Appliances
? Printers
? Smart Toll Systems