| Parameters |
| Mount |
Surface Mount |
| Mounting Type |
Surface Mount |
| Package / Case |
5-TSSOP, SC-70-5, SOT-353 |
| Number of Pins |
5 |
| Operating Temperature |
-55°C~125°C TA |
| Packaging |
Tape & Reel (TR) |
| Series |
74V |
| JESD-609 Code |
e3 |
| Part Status |
Obsolete |
| Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
| Number of Terminations |
5 |
| Type |
D-Type |
| Terminal Finish |
Matte Tin (Sn) |
| Subcategory |
FF/Latches |
| Packing Method |
TAPE AND REEL |
| Technology |
CMOS |
| Voltage - Supply |
2V~5.5V |
| Terminal Position |
DUAL |
| Terminal Form |
GULL WING |
| Peak Reflow Temperature (Cel) |
260 |
| Supply Voltage |
3.3V |
| Time@Peak Reflow Temperature-Max (s) |
30 |
| Base Part Number |
74V1G80 |
| Function |
Standard |
| Qualification Status |
Not Qualified |
| Output Type |
Inverted |
| Polarity |
Inverting |
| Supply Voltage-Min (Vsup) |
2V |
| Number of Circuits |
1 |
| Number of Bits |
1 |
| Clock Frequency |
180MHz |
| Propagation Delay |
12 ns |
| Turn On Delay Time |
4.5 ns |
| Family |
74V |
| Logic Function |
D-Type, Flip-Flop |
| Current - Quiescent (Iq) |
1μA |
| Current - Output High, Low |
8mA 8mA |
| Max I(ol) |
0.004 A |
| Max Propagation Delay @ V, Max CL |
8ns @ 5V, 50pF |
| Trigger Type |
Positive Edge |
| Input Capacitance |
4pF |
| Clock Edge Trigger Type |
Positive Edge |
| Length |
2mm |
| REACH SVHC |
No SVHC |
| RoHS Status |
ROHS3 Compliant |
74V1G80CTR Overview
5-TSSOP, SC-70-5, SOT-353is the packaging method. D flip flop is embedded in the Tape & Reel (TR) package. T flip flop uses Invertedas the output. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. It operates with a supply voltage of 2V~5.5V. In the operating environment, the temperature is -55°C~125°C TA. This D latch has the type D-Type. JK flip flop belongs to the 74Vseries of FPGAs. You should not exceed 180MHzin the output frequency of the device. T flip flop consumes 1μA quiescent energy. A total of 5terminations have been recorded. The 74V1G80family includes it. It is powered from a supply voltage of 3.3V. A 4pFfarad input capacitance is provided by this T flip flop. In this case, the D flip flop belongs to the 74Vfamily. There is an electronic part mounted in the way of Surface Mount. Basically, it is designed with a set of 5 pins. This device has the clock edge trigger type of Positive Edge. The part is included in FF/Latches. The design is based on 1bits. The supply voltage (Vsup) should be maintained above 2V for normal operation. Due to its superior flexibility, it uses 1 circuits. This D flip flop is well suited for TAPE AND REEL based on its reliable performance.
74V1G80CTR Features
Tape & Reel (TR) package
74V series
5 pins
1 Bits
74V1G80CTR Applications
There are a lot of STMicroelectronics 74V1G80CTR Flip Flops applications.
- Computing
- Shift Registers
- Balanced Propagation Delays
- Single Up Count-Control Line
- Single Down Count-Control Line
- Shift registers
- Data Synchronizers
- Power down protection
- Individual Asynchronous Resets
- EMI reduction circuitry