74F821SPC
| Parameters | |
|---|---|
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 9.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Height Seated (Max) | 5.08mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Through Hole |
| Package / Case | 24-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74F |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT APPLICABLE |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT APPLICABLE |
| JESD-30 Code | R-PDIP-T24 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 150MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 100mA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 3mA 24mA |
| Output Polarity | TRUE |
74F821SPC Overview
24-DIP (0.300, 7.62mm)is the way it is packaged. D flip flop is included in the Tubepackage. This output is configured with Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. Through Holeis positioned in the way of this electronic part. A voltage of 4.5V~5.5Vis required for its operation. Temperature is set to 0°C~70°C TA. This D latch has the type D-Type. It is a type of FPGA belonging to the 74F series. Its output frequency should not exceed 150MHz. A total of 1elements are present in it. As a result, it consumes 100mA quiescent current and is not affected by external forces. There have been 24 terminations. Power is supplied from a voltage of 5V volts. Electronic devices of this type belong to the F/FASTfamily. As soon as 5.5Vis reached, Vsup reaches its maximum value. Keeping the supply voltage (Vsup) above 4.5V is necessary for normal operation. The D flip flop is embedded with 2ports.
74F821SPC Features
Tube package
74F series
74F821SPC Applications
There are a lot of Rochester Electronics, LLC 74F821SPC Flip Flops applications.
- Data storage
- Set-reset capability
- Bus hold
- Consumer
- Latch
- CMOS Process
- Parallel data storage
- Data Synchronizers
- Computers
- Dynamic threshold performance