74AUP1G175GF,132
| Parameters | |
|---|---|
| Factory Lead Time | 20 Weeks |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74AUP1G175 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 300MHz |
| Propagation Delay | 19.5 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 21.1 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.7ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.5mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP1G175GF,132 Overview
It is embeded in 6-XFDFN case. The package Tape & Reel (TR)contains it. There is a Non-Invertedoutput configured with it. The trigger it is configured with uses Positive Edge. Surface Mountmounts this electrical part. A supply voltage of 0.8V~3.6V is required for operation. It is operating at a temperature of -40°C~125°C TA. D-Typeis the type of this D latch. JK flip flop belongs to the 74AUPseries of FPGAs. A frequency of 300MHzshould be the maximum output frequency. There have been 6 terminations. The 74AUP1G175 family contains this object. The power supply voltage is 1.2V. Its input capacitance is 0.8pFfarads. AUP/ULP/Vis the family of this D flip flop. It is mounted by the way of Surface Mount. The 6pins are designed into the board. This device exhibits a clock edge trigger type of Positive Edge. 1bits are used in its design. Normally, the supply voltage (Vsup) should be kept above 0.8V. Due to its superior flexibility, it uses 1 circuits. It consumes 500nA current.
74AUP1G175GF,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G175GF,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G175GF,132 Flip Flops applications.
- Power down protection
- Data storage
- 2 – Bit synchronous counter
- Frequency division
- ESD protection
- Balanced Propagation Delays
- Automotive
- Frequency Divider circuits
- Load Control
- ESD performance