74ALVCH16821DGG:11
| Parameters | |
|---|---|
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVCH |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 2.3V~2.7V 3V~3.6V |
| Base Part Number | 74ALVCH16821 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Clock Frequency | 350MHz |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
74ALVCH16821DGG:11 Overview
The flip flop is packaged in a case of 56-TFSOP (0.240, 6.10mm Width). The package Tubecontains it. There is a Tri-State, Non-Invertedoutput configured with it. Positive Edgeis the trigger it is configured with. The electronic part is mounted in the way of Surface Mount. A 2.3V~2.7V 3V~3.6Vsupply voltage is required for it to operate. A temperature of -40°C~85°C TAis used in the operation. Logic flip flops of this type are classified as D-Type. The FPGA belongs to the 74ALVCH series. You should not exceed 350MHzin its output frequency. D latch consists of 2 elements. There is a consumption of 40μAof quiescent energy. The 74ALVCH16821 family contains this object. A JK flip flop with a 5pFfarad input capacitance is used here.
74ALVCH16821DGG:11 Features
Tube package
74ALVCH series
74ALVCH16821DGG:11 Applications
There are a lot of NXP USA Inc. 74ALVCH16821DGG:11 Flip Flops applications.
- ESCC
- Buffered Clock
- Automotive
- Bounce elimination switch
- Memory
- Parallel data storage
- ESD performance
- Data storage
- Asynchronous counter
- Single Down Count-Control Line