74ALVC16821MTD
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVC |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 56 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G56 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 1.65V |
| Number of Ports | 2 |
| Clock Frequency | 250MHz |
| Family | ALVC/VCX/A |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 4ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 6pF |
| Propagation Delay (tpd) | 8.8 ns |
| Length | 14mm |
| Width | 6.1mm |
| RoHS Status | ROHS3 Compliant |
74ALVC16821MTD Overview
It is packaged in the way of 56-TFSOP (0.240, 6.10mm Width). The package Tubecontains it. In the configuration, Tri-State, Non-Invertedis used as the output. This trigger uses the value Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at 1.65V~3.6Vvolts. It is operating at -40°C~85°C TA. D-Typedescribes this flip flop. FPGAs belonging to the 74ALVCseries contain this type of chip. It should not exceed 250MHzin terms of its output frequency. A total of 2elements are present in it. There is a consumption of 40μAof quiescent energy. Terminations are 56. Power is provided by a 1.8V supply. A 6pFfarad input capacitance is provided by this T flip flop. A device of this type belongs to the family of ALVC/VCX/A. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). The supply voltage (Vsup) should be maintained above 1.65V for normal operation. This D flip flop is equipped with 0 ports.
74ALVC16821MTD Features
Tube package
74ALVC series
74ALVC16821MTD Applications
There are a lot of Rochester Electronics, LLC 74ALVC16821MTD Flip Flops applications.
- Registers
- Buffered Clock
- Bounce elimination switch
- Storage registers
- Computers
- Shift registers
- Pattern generators
- Counters
- Common Clocks
- Control circuits