74ACTQ374SC
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACTQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 85MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 9ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 9.5 ns |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74ACTQ374SC Overview
The item is packaged in 20-SOIC (0.295, 7.50mm Width)cases. Package Tubeembeds it. T flip flop is configured with an output of Tri-State, Non-Inverted. JK flip flop uses Positive Edgeas the trigger. There is an electric part mounted in the way of Surface Mount. A voltage of 4.5V~5.5Vis required for its operation. In this case, the operating temperature is -40°C~85°C TA. This D latch has the type D-Type. It is a type of FPGA belonging to the 74ACTQ series. It should not exceed 85MHzin terms of its output frequency. A total of 1elements are contained within it. It consumes 40μA of quiescent current without being affected by external factors. A total of 20 terminations have been made. The D flip flop is powered by a voltage of 5V . JK flip flop input capacitance is 4.5pF farads. A device of this type belongs to the family of ACT. Vsup reaches 5.5V, the maximal supply voltage. A normal operating voltage (Vsup) should remain above 4.5V. There are 2 ports embedded in the flip flops.
74ACTQ374SC Features
Tube package
74ACTQ series
74ACTQ374SC Applications
There are a lot of Rochester Electronics, LLC 74ACTQ374SC Flip Flops applications.
- Bounce elimination switch
- Counters
- 2 – Bit synchronous counter
- Cold spare funcion
- Count Modes
- Common Clocks
- Registers
- Instrumentation
- Control circuits
- Pattern generators