74ACT377SJ
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | WITH HOLD MODE |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 175MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74ACT377SJ Overview
20-SOIC (0.209, 5.30mm Width)is the packaging method. It is contained within the Tubepackage. T flip flop is configured with an output of Non-Inverted. This trigger uses the value Positive Edge. There is an electric part mounted in the way of Surface Mount. It operates with a supply voltage of 4.5V~5.5V. In the operating environment, the temperature is -40°C~85°C TA. D-Typeis the type of this D latch. In this case, it is a type of FPGA belonging to the 74ACT series. A frequency of 175MHzshould be the maximum output frequency. The element count is 1 . There is a consumption of 40μAof quiescent energy. There are 20 terminations,Power is supplied from a voltage of 5V volts. Input capacitance of this device is 4.5pF farads. In this case, the D flip flop belongs to the ACTfamily. There is a 5.5Vmaximum supply voltage (Vsup). The supply voltage (Vsup) should be maintained above 4.5V for normal operation. There is also a characteristic of WITH HOLD MODE.
74ACT377SJ Features
Tube package
74ACT series
74ACT377SJ Applications
There are a lot of Rochester Electronics, LLC 74ACT377SJ Flip Flops applications.
- Common Clocks
- Buffered Clock
- Bounce elimination switch
- Safety Clamp
- Supports Live Insertion
- Cold spare funcion
- Balanced Propagation Delays
- Control circuits
- Frequency division
- Computing