| Parameters |
| Factory Lead Time |
6 Weeks |
| Lifecycle Status |
ACTIVE (Last Updated: 4 days ago) |
| Mount |
Surface Mount |
| Mounting Type |
Surface Mount |
| Package / Case |
20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins |
20 |
| Weight |
76.997305mg |
| Operating Temperature |
-40°C~125°C TA |
| Packaging |
Tape & Reel (TR) |
| Series |
74LV |
| JESD-609 Code |
e4 |
| Pbfree Code |
yes |
| Part Status |
Active |
| Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
| Number of Terminations |
20 |
| ECCN Code |
EAR99 |
| Type |
D-Type |
| Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory |
FF/Latches |
| Packing Method |
TR |
| Technology |
CMOS |
| Voltage - Supply |
4.5V~5.5V |
| Terminal Position |
DUAL |
| Terminal Form |
GULL WING |
| Peak Reflow Temperature (Cel) |
260 |
| Supply Voltage |
2.5V |
| Terminal Pitch |
0.65mm |
| Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
| Base Part Number |
74LV374 |
| Function |
Standard |
| Qualification Status |
Not Qualified |
| Output Type |
Tri-State, Non-Inverted |
| Number of Elements |
1 |
| Polarity |
Non-Inverting |
| Supply Voltage-Max (Vsup) |
5.5V |
| Power Supplies |
3.3V |
| Supply Voltage-Min (Vsup) |
4.5V |
| Number of Circuits |
8 |
| Load Capacitance |
50pF |
| Number of Ports |
2 |
| Output Current |
16mA |
| Number of Bits |
8 |
| Clock Frequency |
150MHz |
| Propagation Delay |
19.3 ns |
| Turn On Delay Time |
4.9 ns |
| Family |
LV/LV-A/LVX/H |
| Logic Function |
D-Type, Flip-Flop |
| Current - Quiescent (Iq) |
2μA |
| Output Characteristics |
3-STATE |
| Current - Output High, Low |
16mA 16mA |
| Max Propagation Delay @ V, Max CL |
10.1ns @ 5V, 50pF |
| Trigger Type |
Positive Edge |
| Input Capacitance |
4pF |
| Number of Input Lines |
2 |
| Count Direction |
UNIDIRECTIONAL |
| Clock Edge Trigger Type |
Positive Edge |
| Translation |
N/A |
| Max Frequency@Nom-Sup |
50000000Hz |
| Height |
1.2mm |
| Length |
6.5mm |
| Width |
4.4mm |
| Thickness |
1mm |
| RoHS Status |
ROHS3 Compliant |
| Lead Free |
Lead Free |
SN74LV374ATPWR Overview
20-TSSOP (0.173, 4.40mm Width)is the packaging method. It is included in the package Tape & Reel (TR). The output it is configured with uses Tri-State, Non-Inverted. It is configured with a trigger that uses Positive Edge. Surface Mountis occupied by this electronic component. With a supply voltage of 4.5V~5.5V volts, it operates. A temperature of -40°C~125°C TAis considered to be the operating temperature. D-Typedescribes this flip flop. This type of FPGA is a part of the 74LV series. There should be no greater frequency than 150MHzon its output. There are 1 elements in it. As a result, it consumes 2μA of quiescent current without being affected by external factors. A total of 20terminations have been recorded. It is a member of the 74LV374 family. Power is supplied from a voltage of 2.5V volts. A JK flip flop with a 4pFfarad input capacitance is used here. The electronic device belongs to the LV/LV-A/LVX/Hfamily. Surface Mount mounts this electronic component. It is designed with 20 pins. This device exhibits a clock edge trigger type of Positive Edge. There is a base part number FF/Latchesfor the RS flip flops. This flip flop is designed with 8 Bits. There is a 5.5Vmaximum supply voltage (Vsup). The supply voltage (Vsup) should be kept above 4.5V for normal operation. Its superior flexibility is attributed to its use of 8 circuits. In view of its reliability, this D flip flop is a good fit for TR. It operates from 3.3V power supplies. The D flip flop is embedded with 2ports. The output current of 16mA makes it feature maximum design flexibility. This input has 2lines in it.
SN74LV374ATPWR Features
Tape & Reel (TR) package
74LV series
20 pins
8 Bits
3.3V power supplies
SN74LV374ATPWR Applications
There are a lot of Texas Instruments SN74LV374ATPWR Flip Flops applications.
- Common Clocks
- Supports Live Insertion
- Power down protection
- Asynchronous counter
- Individual Asynchronous Resets
- Matched Rise and Fall
- Patented noise
- Single Up Count-Control Line
- Automotive
- Clock pulse