SN74AUP1G80DRYR
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-UFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74AUP1G80 |
| Function | Standard |
| Number of Outputs | 1 |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Load Capacitance | 30pF |
| Number of Bits | 1 |
| Clock Frequency | 260MHz |
| Propagation Delay | 6.4 ns |
| Turn On Delay Time | 3.1 ns |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 0.9μA |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Prop. Delay@Nom-Sup | 28.7 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Height | 600μm |
| Length | 1.45mm |
| Width | 1mm |
| Thickness | 500μm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP1G80DRYR Overview
It is embeded in 6-UFDFN case. A package named Tape & Reel (TR)includes it. T flip flop uses Invertedas the output. It is configured with the trigger Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A supply voltage of 0.8V~3.6V is required for operation. It is at -40°C~85°C TAdegrees Celsius that the system is operating. Logic flip flops of this type are classified as D-Type. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. A frequency of 260MHzshould not be exceeded by its output. As a result, it consumes 0.9μA quiescent current. There have been 6 terminations. If you search by 74AUP1G80, you will find similar parts. Power is provided by a 1.2V supply. The input capacitance of this T flip flop is 1.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. A device of this type belongs to the family of AUP/ULP/V. It is mounted by the way of Surface Mount. As you can see from the design, it has pins with 6. It has a clock edge trigger type of Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. The flip flop is designed with 1bits. Normally, the supply voltage (Vsup) should be kept above 0.8V. As a result of its reliable performance, this T flip flop is suitable for TR.
SN74AUP1G80DRYR Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
SN74AUP1G80DRYR Applications
There are a lot of Texas Instruments SN74AUP1G80DRYR Flip Flops applications.
- Frequency Divider circuits
- Buffered Clock
- EMI reduction circuitry
- Divide a clock signal by 2 or 4
- Convert a momentary switch to a toggle switch
- Bounce elimination switch
- Parallel data storage
- Balanced 24 mA output drivers
- ESD performance
- Frequency division