SN74AHC74QDRQ1
| Parameters | |
|---|---|
| Current - Output High, Low | 8mA 8mA |
| Max I(ol) | 0.008 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 9.3ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 2pF |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 75000000Hz |
| Height | 1.75mm |
| Length | 8.65mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Weight | 122.413241mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | Automotive, AEC-Q100, 74AHC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Base Part Number | 74AHC74 |
| Function | Set(Preset) and Reset |
| Number of Outputs | 4 |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 8mA |
| Clock Frequency | 115MHz |
| Propagation Delay | 15.4 ns |
| Turn On Delay Time | 1 ns |
| Family | AHC/VHC/H/U/V |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 2μA |
SN74AHC74QDRQ1 Overview
It is packaged in the way of 14-SOIC (0.154, 3.90mm Width). You can find it in the Tape & Reel (TR)package. In the configuration, Differentialis used as the output. It is configured with a trigger that uses a value of Positive Edge. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates at 2V~5.5Vvolts. -40°C~125°C TAis the operating temperature. Logic flip flops of this type are classified as D-Type. FPGAs belonging to the Automotive, AEC-Q100, 74AHCseries contain this type of chip. It should not exceed 115MHzin its output frequency. T flip flop consumes 2μA quiescent energy. The number of terminations is 14. JK flip flop belongs to 74AHC74 family. It is powered by a voltage of 3.3V . A 2pFfarad input capacitance is provided by this T flip flop. AHC/VHC/H/U/Vis the family of this D flip flop. Electronic part Surface Mountis mounted in the way. 14pins are included in its design. Its clock edge trigger type is Positive Edge. The part is included in FF/Latches. The maximal supply voltage (Vsup) reaches 5.5V. The supply voltage (Vsup) should be maintained above 2V for normal operation. 2 circuits are used to achieve its superior flexibility. Considering its reliability, this T flip flop is well suited for TR. With an output current of 8mA, this device offers maximum design flexibility.
SN74AHC74QDRQ1 Features
Tape & Reel (TR) package
Automotive, AEC-Q100, 74AHC series
14 pins
SN74AHC74QDRQ1 Applications
There are a lot of Texas Instruments SN74AHC74QDRQ1 Flip Flops applications.
- Load Control
- Bounce elimination switch
- Modulo – n – counter
- Circuit Design
- Power down protection
- Counters
- Communications
- 2 – Bit synchronous counter
- Functionally equivalent to the MC10/100EL29
- Cold spare funcion