| Parameters | |
|---|---|
| Factory Lead Time | 12 Weeks |
| Package / Case | 740-LBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Published | 2002 |
| Series | MPC83xx |
| JESD-609 Code | e1 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 740 |
| ECCN Code | 5A002.A.1 |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| HTS Code | 8542.31.00.01 |
| Subcategory | Microprocessors |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.3V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | MPC8360 |
| JESD-30 Code | S-PBGA-B740 |
| Supply Voltage-Max (Vsup) | 1.35V |
| Power Supplies | 1.8/2.53.3V |
| Supply Voltage-Min (Vsup) | 1.25V |
| Speed | 667MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC e300 |
| Clock Frequency | 66.67MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 32 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 1.8V 2.5V 3.3V |
| Ethernet | 10/100/1000Mbps (1) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DDR, DDR2 |
| USB | USB 1.x (1) |
| Additional Interfaces | DUART, HDLC, I2C, PCI, SPI, UART |
| Co-Processors/DSP | Communications; QUICC Engine, Security; SEC |
| Security Features | Cryptography, Random Number Generator |
| Height Seated (Max) | 1.69mm |
| Length | 37.5mm |
| RoHS Status | ROHS3 Compliant |
MPC8360EVVALFHA PowerQUICC? II Pro family of integrated communications processors is a next-generation extension of the popular PowerQUICC II line containing cores built on Power Architecture? technology. The MPC8360EVVALFHA incorporates a next-generation communications engine, the QUICC Engine?. supporting a wide range of protocols, including Gigabit Ethernet (GbE) and OC-12 asynchronous transfer mode (ATM)/packet over SONET (POS). Additional enhancements include the e300 core (enhanced version of the 603e? core with larger caches), scaling up to 667 MHz, a double data rate (DDR) memory controller, and the integrated security engine.
e300 PowerPC processor core (enhanced version of the MPC603e core)
Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the MPC8358E
PCI interface
QUICC Engine unit
The security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i?, iSCSI, and IKE processing.
Motorcycle Engine Control Unit (ECU) and Small Engine Control
Broadband Modem and Residential Gateway
Surround View
POS Terminal
Small and Medium Appliances