HEF40374BT,652
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 4000B |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 3V~15V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 40374 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Min (Vsup) | 3V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 17MHz |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 50mA 62mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 80ns @ 15V, 50pF |
| Prop. Delay@Nom-Sup | 250 ns |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 250 ns |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
HEF40374BT,652 Overview
20-SOIC (0.295, 7.50mm Width)is the way it is packaged. Package Tubeembeds it. T flip flop is configured with an output of Tri-State, Non-Inverted. In the configuration of the trigger, Positive Edgeis used. It is mounted in the way of Surface Mount. It operates with a supply voltage of 3V~15V. A temperature of -40°C~85°C TAis used in the operation. This electronic flip flop is of type D-Type. The FPGA belongs to the 4000B series. It should not exceed 17MHzin its output frequency. In total, there are 1 elements. A total of 20terminations have been recorded. This D latch belongs to the family of 40374. The D flip flop is powered by a voltage of 5V . This device is part of the FF/Latchesbase part number family. For normal operation, the supply voltage (Vsup) should be above 3V. A D flip flop with 2embedded ports is available.
HEF40374BT,652 Features
Tube package
4000B series
HEF40374BT,652 Applications
There are a lot of NXP USA Inc. HEF40374BT,652 Flip Flops applications.
- Frequency Divider circuits
- ATE
- ESCC
- Patented noise
- Latch-up performance
- Circuit Design
- Latch
- Count Modes
- Registers
- Shift Registers