EPM7064SLC84-10N
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 84-LCC (J-Lead) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | MAX® 7000S |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 84 |
| ECCN Code | EAR99 |
| Terminal Finish | Matte Tin (Sn) |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Reach Compliance Code | compliant |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | EPM7064 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 3.3/55V |
| Programmable Type | In System Programmable |
| Number of I/O | 68 |
| Clock Frequency | 125MHz |
| Propagation Delay | 10 ns |
| Number of Gates | 1250 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | NO |
| Voltage Supply - Internal | 4.75V~5.25V |
| Delay Time tpd(1) Max | 10ns |
| Number of Logic Elements/Blocks | 4 |
| Height Seated (Max) | 5.08mm |
| Length | 29.3116mm |
| Width | 29.3116mm |
| RoHS Status | RoHS Compliant |
EPM7064SLC84-10N Overview
64macrocells exist, which are cells in a mobile phone network that are primarily composed of high-power towers, antennas, or masts.The item is packaged with 84-LCC (J-Lead).As a result, it has 68 I/O ports programmed.It is programmed that device terminations will be 84 .Its terminal position is QUAD.Power is provided by a supply voltage of 5V volts.This part is included in Programmable Logic Devices.It is packaged in the way of Tray.It operates with the operating temperature of 0°C~70°C TA to ensure its reliability.Surface Mountshould be used for mounting the chip.In terms of FPGAs, it belongs to the MAX? 7000S series.When using this device, CONFIGURABLE I/O OPERATION WITH 3.3V OR 5Vis also available.There are related parts in [0].It is possible to construct digital circuits using 1250gates, which are devices that serve as building blocks.A total of 4logic elements/blocks are present.There is 3.3/55V power supply available for it.The maximal supply voltage (Vsup) reaches 5.25V.Its clock frequency should not exceed 125MHz.
EPM7064SLC84-10N Features
84-LCC (J-Lead) package
68 I/Os
The operating temperature of 0°C~70°C TA
3.3/55V power supplies
EPM7064SLC84-10N Applications
There are a lot of Intel EPM7064SLC84-10N CPLDs applications.
- Software-driven hardware configuration
- Digital designs
- Protection relays
- Multiple DIP Switch Replacement
- Software Configuration of Add-In Boards
- Code converters
- Reset swapping
- Preset swapping
- State machine design
- Synchronous or asynchronous mode