74LVT273PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Clock Frequency | 150MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 5.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 5.9 ns |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVT273PW,112 Overview
20-TSSOP (0.173, 4.40mm Width)is the way it is packaged. The Tubepackage contains it. Non-Invertedis the output configured for it. There is a trigger configured with Positive Edge. There is an electric part mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. In the operating environment, the temperature is -40°C~85°C TA. A flip flop of this type is classified as a D-Type. JK flip flop belongs to the 74LVTseries of FPGAs. It should not exceed 150MHzin terms of its output frequency. D latch consists of 1 elements. This process consumes 190μA quiescents. There are 20 terminations,D latch belongs to the 74LVT273 family. Power is provided by a 3.3V supply. This JK flip flop has a 4pFfarad input capacitance. This D flip flop belongs to the family of LVT. The part you are looking for is included in FF/Latches. In this case, the maximum supply voltage (Vsup) reaches 3.6V. For normal operation, the supply voltage (Vsup) should be kept above 2.7V. The system runs on a power supply of 3.3V watts.
74LVT273PW,112 Features
Tube package
74LVT series
3.3V power supplies
74LVT273PW,112 Applications
There are a lot of NXP USA Inc. 74LVT273PW,112 Flip Flops applications.
- Latch-up performance
- Event Detectors
- Digital electronics systems
- Load Control
- Guaranteed simultaneous switching noise level
- Communications
- Balanced 24 mA output drivers
- Reduced system switching noise
- Computers
- Registers