| Parameters |
| Contact Plating |
Gold |
| Mount |
Surface Mount |
| Mounting Type |
Surface Mount |
| Package / Case |
24-SSOP (0.209, 5.30mm Width) |
| Number of Pins |
24 |
| Operating Temperature |
-40°C~125°C TA |
| Packaging |
Tube |
| Series |
74LVC |
| JESD-609 Code |
e4 |
| Part Status |
Not For New Designs |
| Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
| Number of Terminations |
24 |
| Type |
D-Type |
| Additional Feature |
WITH CLEAR AND CLOCK ENABLE |
| Technology |
CMOS |
| Voltage - Supply |
1.65V~3.6V |
| Terminal Position |
DUAL |
| Terminal Form |
GULL WING |
| Peak Reflow Temperature (Cel) |
260 |
| Supply Voltage |
1.8V |
| Terminal Pitch |
0.65mm |
| Time@Peak Reflow Temperature-Max (s) |
30 |
| Base Part Number |
74LVC823 |
| Function |
Master Reset |
| Output Type |
Tri-State, Non-Inverted |
| Number of Elements |
1 |
| Polarity |
Non-Inverting |
| Supply Voltage-Max (Vsup) |
3.6V |
| Number of Ports |
2 |
| Number of Bits |
9 |
| Clock Frequency |
200MHz |
| Propagation Delay |
5.1 ns |
| Quiescent Current |
100μA |
| Turn On Delay Time |
3.7 ns |
| Family |
LVC/LCX/Z |
| Logic Function |
D-Type, Flip-Flop |
| Current - Quiescent (Iq) |
10μA |
| Output Characteristics |
3-STATE |
| Current - Output High, Low |
24mA 24mA |
| Max Propagation Delay @ V, Max CL |
10ns @ 3.3V, 50pF |
| Trigger Type |
Positive Edge |
| Input Capacitance |
5pF |
| Number of Input Lines |
9 |
| Clock Edge Trigger Type |
Positive Edge |
| Height Seated (Max) |
2mm |
| Length |
8.2mm |
| Width |
5.3mm |
| Radiation Hardening |
No |
| RoHS Status |
ROHS3 Compliant |
74LVC823ADB,112 Overview
24-SSOP (0.209, 5.30mm Width)is the way it is packaged. The package Tubecontains it. The output it is configured with uses Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A voltage of 1.65V~3.6Vis used as the supply voltage. A temperature of -40°C~125°C TAis used in the operation. D-Typedescribes this flip flop. In this case, it is a type of FPGA belonging to the 74LVC series. You should not exceed 200MHzin its output frequency. There are 1 elements in it. This process consumes 10μA quiescents. Currently, there are 24 terminations. D latch belongs to the 74LVC823 family. A voltage of 1.8V is used as the power supply for this D latch. Its input capacitance is 5pF farads. Electronic devices of this type belong to the LVC/LCX/Zfamily. There is an electronic part mounted in the way of Surface Mount. This board is designed with 24pins on it. A Positive Edgeclock edge trigger is used in this device. It is designed with 9bits. It reaches the maximum supply voltage (Vsup) at 3.6V. The D flip flop has no ports embedded. 9input lines are available for you to choose from. Quiescent current is consumed by the D latch in the amount of 100μA. WITH CLEAR AND CLOCK ENABLEis also one of its characteristics.
74LVC823ADB,112 Features
Tube package
74LVC series
24 pins
9 Bits
74LVC823ADB,112 Applications
There are a lot of Nexperia USA Inc. 74LVC823ADB,112 Flip Flops applications.
- Synchronous counter
- Circuit Design
- Differential Individual
- Dynamic threshold performance
- Buffer registers
- Balanced Propagation Delays
- Guaranteed simultaneous switching noise level
- Computers
- EMI reduction circuitry
- Single Down Count-Control Line