74LVC574APW,112
| Parameters | |
|---|---|
| Factory Lead Time | 4 Weeks |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Additional Feature | BROADSIDE VERSION OF 374 |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74LVC574 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Number of Bits | 8 |
| Clock Frequency | 200MHz |
| Propagation Delay | 3.2 ns |
| Quiescent Current | 100nA |
| Turn On Delay Time | 9 ns |
| Family | LVC/LCX/Z |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Input Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 950μm |
| Length | 6.6mm |
| Width | 4.5mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74LVC574APW,112 Overview
It is packaged in the way of 20-TSSOP (0.173, 4.40mm Width). A package named Tubeincludes it. There is a Tri-State, Non-Invertedoutput configured with it. This trigger uses the value Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. With a supply voltage of 1.65V~3.6V volts, it operates. In this case, the operating temperature is -40°C~125°C TA. This D latch has the type D-Type. The 74LVCseries comprises this type of FPGA. Its output frequency should not exceed 200MHz. D latch consists of 1 elements. As a result, it consumes 10μA of quiescent current without being affected by external factors. There are 20 terminations,If you search by 74LVC574, you will find similar parts. A voltage of 2.7V is used as the power supply for this D latch. This T flip flop has a capacitance of 5pF farads at the input. Electronic devices of this type belong to the LVC/LCX/Zfamily. There is an electronic part that is mounted in the way of Surface Mount. With its 20pins, it is designed to work with most electronic flip flops. There is a clock edge trigger type of Positive Edgeon this device. This flip flop is designed with 8 Bits. In this case, the maximum supply voltage (Vsup) reaches 3.6V. The flip flop has 2embedded ports. Currently, there are 8 lines of input. As a result, it consumes 100nA of quiescent current without being affected by external factors. In addition, you can refer to the additinal BROADSIDE VERSION OF 374 of the D latch.
74LVC574APW,112 Features
Tube package
74LVC series
20 pins
8 Bits
74LVC574APW,112 Applications
There are a lot of Nexperia USA Inc. 74LVC574APW,112 Flip Flops applications.
- Reduced system switching noise
- ESD performance
- Data transfer
- Parallel data storage
- Event Detectors
- Matched Rise and Fall
- Computing
- Differential Individual
- Storage Registers
- Supports Live Insertion