74LVC109PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 2002 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC109 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Clock Frequency | 330MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.8ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 7.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 7.5 ns |
| Length | 5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVC109PW,112 Overview
The item is packaged in 16-TSSOP (0.173, 4.40mm Width)cases. A package named Tubeincludes it. It is configured with Differentialas an output. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. With a supply voltage of 1.65V~3.6V volts, it operates. Temperature is set to -40°C~125°C TA. This electronic flip flop is of type JK Type. The FPGA belongs to the 74LVC series. There should be no greater frequency than 330MHzon its output. In total, there are 2 elements. It consumes 10μA of quiescent The number of terminations is 16. The 74LVC109family includes it. An input voltage of 3.3Vpowers the D latch. Its input capacitance is 5pFfarads. LVC/LCX/Zis the family of this D flip flop. This device has the base part number FF/Latches. Vsup reaches 3.6V, the maximal supply voltage. The system runs on a power supply of 3.3V watts.
74LVC109PW,112 Features
Tube package
74LVC series
3.3V power supplies
74LVC109PW,112 Applications
There are a lot of NXP USA Inc. 74LVC109PW,112 Flip Flops applications.
- Common Clocks
- Reduced system switching noise
- ESCC
- Frequency Divider circuits
- Buffer registers
- ESD protection
- Control circuits
- Cold spare funcion
- Data transfer
- Single Down Count-Control Line