74AUP2G80DC,125
| Parameters | |
|---|---|
| Factory Lead Time | 8 Weeks |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-VFSOP (0.091, 2.30mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74AUP2G80 |
| Function | Standard |
| Output Type | Inverted |
| Polarity | Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Circuits | 2 |
| Output Current | 20mA |
| Clock Frequency | 309MHz |
| Propagation Delay | 20.7 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
74AUP2G80DC,125 Overview
The flip flop is packaged in a case of 8-VFSOP (0.091, 2.30mm Width). Package Tape & Reel (TR)embeds it. T flip flop is configured with an output of Inverted. This trigger is configured to use Positive Edge. This electronic part is mounted in the way of Surface Mount. A 0.8V~3.6Vsupply voltage is required for it to operate. It is operating at a temperature of -40°C~125°C TA. A flip flop of this type is classified as a D-Type. In this case, it is a type of FPGA belonging to the 74AUP series. In order for it to function properly, its output frequency should not exceed 309MHz. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. D latch belongs to the 74AUP2G80 family. An input voltage of 1.2Vpowers the D latch. A JK flip flop with a 0.6pFfarad input capacitance is used here. AUP/ULP/Vis the family of this D flip flop. The electronic part is mounted in the way of Surface Mount. This board has 8 pins. This device's clock edge trigger type is Positive Edge. There is a 3.6Vmaximum supply voltage (Vsup). The superior flexibility of this circuit is achieved by using 2 circuits. The output current of 20mA makes it feature maximum design flexibility. It has 1 output lines to operate. This D latch consumes 500nA quiescent current at all.
74AUP2G80DC,125 Features
Tape & Reel (TR) package
74AUP series
8 pins
74AUP2G80DC,125 Applications
There are a lot of Nexperia USA Inc. 74AUP2G80DC,125 Flip Flops applications.
- QML qualified product
- Balanced 24 mA output drivers
- Convert a momentary switch to a toggle switch
- Instrumentation
- Computers
- Buffered Clock
- Safety Clamp
- Memory
- Bounce elimination switch
- Reduced system switching noise